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order number: mpc106ec/d rev. 5, 8/2001 semiconductor products sector this document contains information on a new product under development by motorola. motorola reserves the right to change or discontinue this product without notice. ?motorola, inc., 2001. all rights reserved. technical data mpc106 pci bridge/memory controller hardware speci?ations the motorola mpc106 pci bridge/memory controller provides a powerpc microprocessor common hardware reference platform (chrp) compliant bridge between the powerpc microprocessor family and the peripheral component interconnect (pci) bus. in this document, the term ?06 is used as an abbreviation for the phrase ?pc106 pci bridge/memory controller. this document contains pertinent physical characteristics of the 106. for functional characteristics, refer to the mpc106 pci bridge/memory controller users manual . this document contains the following topics: topic page section 1.1, ?verview 2 section 1.2, ?eatures 3 section 1.3, ?eneral parameters 5 section 1.4, ?lectrical and thermal characteristics 5 section 1.5, ?in assignments 15 section 1.6, ?inout listings 16 section 1.7, ?ackage description 20 section 1.8, ?ystem design information 22 section 1.9, ?ocument revision history 27 section 1.10, ?rdering information 27
2 mpc106 pci bridge/memory controller hardware speci?ations overview in this document, the term ?0x is used to denote a 32-bit microprocessor from the powerpc architecture family that conforms to the bus interface of the powerpc 601, powerpc 603, or powerpc 604 microprocessors. note that this does not include the powerpc 602 microprocessor which has a multiplexed address/data bus. 60x processors implement the powerpc architecture as it is speci?d for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and ?ating-point data types of 32 and 64 bits (single-precision and double-precision). to locate any published errata or updates for this document, refer to the website at http://www.mot.com/sps/powerpc/. 1.1 overview the mpc106 provides an integrated high-bandwidth, high-performance, ttl-compatible interface between a 60x processor, a secondary (l2) cache or additional (up to four total) 60x processors, the pci bus, and main memory. this section provides a block diagram showing the major functional units of the 106 and describes brie? how those units interact. figure 1 shows the major functional units within the 106. note that this is a conceptual block diagram intended to show the basic features rather than how these features are physically implemented on the device. figure 1. block diagram target master pci interface pci bus memory interface power management error/interrupt control configuration registers l2 60x processor interface l2 cache interface 60x bus memory
mpc106 pci bridge/memory controller hardware speci?ations 3 features the 106 provides a powerpc microprocessor chrp-compliant bridge between the powerpc microprocessor family and the pci bus. chrp documentation provides a set of speci?ations that de?e a uni?d personal computer architecture. pci support allows the rapid design of systems using peripherals already designed for pci and the other standard interfaces available in the personal computer hardware environment. the 106 integrates secondary cache control and a high-performance memory controller, uses an advanced, 3.3-v cmos process technology, and is fully compatible with ttl devices. the 106 supports a programmable interface to a variety of powerpc microprocessors operating at select bus speeds. the 60x address bus is 32 bits wide and the data bus is 64 bits wide. the 60x processor interface of the 106 uses a subset of the 60x bus protocol, supporting single-beat and burst data transfers. the address and data buses are decoupled to support pipelined transactions. the 106 provides support for the following con?urations of 60x processors and l2 cache: up to four 60x processors with no l2 cache a single 60x processor plus a direct-mapped, lookaside l2 cache using the internal l2 cache controller of the 106 up to four 60x processors plus an externally controlled l2 cache (such as the motorola mpc2605 integrated secondary cache) the memory interface controls processor and pci interactions to main memory and is capable of supporting a variety of con?urations using dram, edo, sdram, rom, or flash rom. the pci interface of the 106 complies with the pci local bus speci?ation, revision 2.1, and follows the guidelines in the pci system design guide, revision 1.0, for host bridge architecture. the pci interface connects the processor and memory buses to the pci bus, to which i/o components are connected. the pci bus uses a 32-bit multiplexed address/data bus, plus various control and error signals. the pci interface of the 106 functions as both a master and target device. as a master, the 106 supports read and write operations to the pci memory space, the pci i/o space, and the pci con?uration space. the 106 also supports pci special-cycle and interrupt-acknowledge commands. as a target, the 106 supports read and write operations to system memory. the 106 provides hardware support for four levels of power reduction: doze, nap, sleep, and suspend. the design of the mpc106 is fully static, allowing internal logic states to be preserved during all power-saving modes. 1.2 features this section summarizes the major features of the 106, as follows: 60x processor interface supports up to four 60x processors supports various operating frequencies and bus divider ratios 32-bit address bus, 64-bit data bus supports full memory coherency supports optional 60x local bus slave decoupled address and data buses for pipelining of 60x accesses store gathering on 60x-to-pci writes
4 mpc106 pci bridge/memory controller hardware speci?ations features secondary (l2) cache control con?urable for write-through or write-back operation supports cache sizes of 256 kbytes, 512 kbytes, and 1 mbyte up to 4 gbytes of cacheable space direct-mapped supports byte parity supports partial update with external byte decode for write enables programmable interface timing supports pipelined burst, synchronous burst, or asynchronous srams alternately supports an external l2 cache controller or integrated l2 cache module memory interface 1 gbyte of ram space, 16 mbytes of rom space supports parity or error checking and correction (ecc) high-bandwidth, 64-bit data bus (72 bits including parity or ecc) supports fast page mode drams, extended data out (edo) drams, and synchronous drams (sdrams) supports 1 to 8 banks of dram/edo/sdram with sizes ranging from 2 mbyte to 128 mbytes per bank rom space may be split between the pci bus and the 60x/memory bus (8 mbytes each) supports 8-bit asynchronous rom or 64-bit burst-mode rom supports writing to flash rom con?urable external buffer control logic programmable interface timing pci interface compliant with pci local bus speci?ation, revision 2.1 supports pci interlocked accesses to memory using lock signal and protocol supports accesses to all pci address spaces selectable big- or little-endian operation store gathering on pci writes to memory selectable memory prefetching of pci read accesses only one external load presented by the mpc106 to the pci bus interface operates at 20?3 mhz word parity supported 3.3 v/5.0 v-compatible support for concurrent transactions on 60x and pci buses power management fully-static 3.3-v cmos design supports 60x nap, doze, and sleep power management modes and suspend mode ieee 1149.1-compliant, jtag boundary-scan interface 304-pin ceramic ball grid array (cbga) package
mpc106 pci bridge/memory controller hardware speci?ations 5 general parameters 1.3 general parameters the following list provides a summary of the general parameters of the 106: technology 0.5 ? cmos, four-layer metal die size 5.8 mm x 7.2 mm (41.8 mm 2 ) transistor count 250,000 logic design fully-static packages surface mount 304-lead c4 ceramic ball grid array (cbga) power supply 3.3 v ?5% v dc maximum input rating 5.0 v ?10% v dc 1.4 electrical and thermal characteristics this section provides both the ac and dc electrical speci?ations and thermal characteristics for the 106. 1.4.1 dc electrical characteristics the tables in this section describe the 106 dc electrical characteristics. table 1 provides the absolute maximum ratings. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause it permanent damage. table 2 provides the recommended operating conditions for the 106. proper device operation outside of these recommended and tested conditions is not guaranteed. table 1. absolute maximum ratings characteristic symbol value unit notes supply voltage vdd ?.3 to 3.6 v pll supply voltage avdd ?.3 to 3.6 v input voltage v in ?.3 to 5.5 v 1 junction temperature t j 0 to 105 ? 2 storage temperature range t stg ?5 to 150 ? notes : 1 caution : v in must not exceed vdd by more than 2.5 v at all times including during power-on reset. 2 the extended temperature parts have die junction temperature of -40 to 105?. see mpc106arxtgpns/d for more information.
6 mpc106 pci bridge/memory controller hardware speci?ations electrical and thermal characteristics table 3 provides the package thermal characteristics for the 106. table 4 provides the dc electrical characteristics for the 106, assuming vdd = avdd = 3.3 ?5% v dc, gnd = 0 v dc, and 0 t j 105 ?. table 5 lists the power consumption of the 106. table 2. recommended operating conditions characteristic symbol value unit notes supply voltage vdd 3.3 ?165 mv v pll supply voltage avdd 3.3 ?165 mv v input voltage v in 0 to 5.5 v die junction temperature t j 0 to 105 ? the extended temperature parts have die junction temperature of -40 to 105? table 3. package thermal characteristics characteristic symbol value rating cbga package thermal resistance, junction-to-top of die jc 0.133 ?/w note : refer to section 1.8, ?ystem design information, for more details about thermal management. table 4. dc electrical specifications characteristic symbol min max unit input high voltage (all inputs except sysclk) v ih 2 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current, v in =3.3 v 1 i in 15.0 ? hi-z (off-state) leakage current, v in = 3.3 v 1 i tsi 15.0 ? output high voltage, i oh = -7 ma 2 v oh 2.4 v output low voltage, i ol = 7 ma 2 v ol 0.5 v pci 3.3 v signaling output high voltage, i oh = -0.5 ma 2 v oh 2.7 v pci 3.3 v signaling output low voltage, i ol = 1.5 ma 2 v ol 0.3 v capacitance, v in = 0 v, f = 1 mhz 3 c in 7.0 pf notes: 1 excludes test signals (lssd_mode and jtag signals). 2 this value represents worst case 40-ohm drivers (default value for processor/l2 control signals ci , wt , gbl , tbst , tsiz[0?], tt[0?], twe , and tv ) only. other signals have lower default driver impedance and will support larger i oh and i ol . all drivers may optionally be programmed to different driver strengths. 3 capacitance is periodically sampled rather than 100% tested.
mpc106 pci bridge/memory controller hardware speci?ations 7 electrical and thermal characteristics 1.4.2 ac electrical characteristics this section provides ac electrical characteristics for the 106. after fabrication, parts are sorted by maximum 60x processor bus frequency, as shown in section 1.4.2.1, ?lock ac speci?ations,?and tested for conformance to the ac speci?ations for that frequency. these speci?ations are for operation between 16.67 and 33.33 mhz pci bus (sysclk) frequencies. the 60x processor bus frequency is determined by the pci bus (sysclk) frequency and the settings of the pll[0?] signals. all timings are speci?d relative to the rising edge of sysclk. 1.4.2.1 clock ac speci?ations table 6 provides the clock ac timing speci?ations as shown in figure 2, and assumes vdd = avdd = 3.3 ?5% v dc, gnd = 0 v dc, and 0 t j 105 ?. table 5. power consumption mode sysclk/core 33/66 mhz sysclk/core 33/83.3 mhz unit full-on typical maximum 1.2 2.2 w 1.4 2.4 w doze typical maximum 1.0 1.1 w 1.2 1.4 w nap typical maximum 1.0 1.1 w 1.2 1.4 w sleep typical maximum 260 330 mw 360 450 mw suspend typical maximum 140 220 mw 190 270 mw notes: power consumption for common system con?urations assuming 50 pf loads suspend power-saving mode assumes sysclk off and pll in bypass mode. typical power is an average value measured at vdd = avdd = 3.30 v and t a = 25 ?. maximum power is measured at vdd = avdd = 3.45 v and t a = 25 ?.
8 mpc106 pci bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 2 provides the sysclk input timing diagram. figure 2. sysclk input timing diagram 1.4.2.2 input ac speci?ations table 7 provides the input ac timing speci?ations for the 106 as de?ed in figure 3 and figure 4. these speci?ations are for operation between 16.67 and 33.33 mhz pci bus clock (sysclk) frequencies. assume vdd = avdd = 3.3 ?5% v dc, gnd = 0 v dc, and 0 t j 105 ?. table 6. clock ac timing specifications num characteristic sysclk/core 33/66 mhz sysclk/core 33/83.3 mhz unit notes min max min max 60x processor bus (core) frequency 16.67 66 16.67 83.3 mhz 1 vco frequency 120 200 120 200 mhz 1, 2 sysclk frequency 16.67 33.33 16.67 33.33 mhz 1 1 sysclk cycle time 30.0 60.0 30.0 60.0 ns 2, 3 sysclk rise and fall time 2.0 2.0 ns 3 4 sysclk duty cycle measured at 1.4 v 40 60 40 60 % 4 sysclk jitter ?00 ?00 ps 5 106 internal pll relock time 100 100 s 4, 6 notes : 1 caution : the sysclk frequency and pll[0?] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll[0?] signal description in section 1.8, ?ystem design information, for valid pll[0?] settings, and to section 1.9, ?ocument revision history, for available frequencies and part numbers. 2 vco operating range for extended temperature devices is different. refer to mpc106arxtgpns/d for more information. 3 rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 4 timing is guaranteed by design and characterization and is not tested. 5 the total input jitter (short-term and long-term combined) must be under ?00 ps. 6 pll-relock time is the maximum time required for pll lock after a stable vdd, avdd, and sysclk are reached during the power-on reset sequence. this speci?ation also applies when the pll has been disabled and subsequently re-enabled during the sleep and suspend power-saving modes. also note that hrst must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 s) during the power-on reset sequence. vm vm = midpoint voltage (1.4 v) 2 3 cv il cv ih 1 sysclk vm vm 4 4
mpc106 pci bridge/memory controller hardware speci?ations 9 electrical and thermal characteristics figure 3 provides the input timing diagram for the 106. table 7. input ac timing specifications num characteristic 66 mhz 83.3 mhz unit notes min max min max 10a group i input signals valid to 60x bus clock (input setup) 4.0 3.5 ns 1,2,3 10a group ii input signals valid to 60x bus clock (input setup) 3.5 3.5 ns 1,2,4 10a group iii input signals valid to 60x bus clock (input setup) 3.0 2.5 ns 1,2,5 10a group iv input signals valid to 60x bus clock (input setup) 5.0 4.0 ns 1,2,6 10b group v input signals valid to sysclk (input setup) 7.0 7.0 ns 7,8 10b group vi input signals valid to sysclk (input setup) 7.0 7.0 ns 7,9 11a 60x bus clock to group i?v inputs invalid (input hold) 0 0 ns 3,4,5,6 11b sysclk to group v?i inputs invalid (input hold) ?.5 ?.5 ns 8,9 hrst pulse width 255 x t sysclk + 100 ? 255 x t sysclk + 100 ? 10c mode select inputs valid to hrst (input setup) 3 x t sysclk 3 x t sysclk ns 10, 11,12 11c hrst to mode select input invalid (input hold) 1.0 1.0 ns 10, 12 notes: 1 input speci?ations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of sysclk. both input and output timings are measured at the pin (see figure 3). 2 processor and memory interface signals are speci?d from the rising edge of the 60x bus clock (which is internally synchronized to sysclk). 3 group i input signals include the following processor, l2, and memory interface signals: a[0?1], par[0?]/ar[1?], br [0?], brl2 , xa ts , lbclaim , ads , ba0, tv and hit (when con?ured for external l2) 4 group ii input signals include the following processor and memory interface signals: tbst , tt[0?], tsiz[0?], wt , ci , gbl , aa ck , and t a . 5 group iii input signals include the following processor and memory interface signals: dl[0?1] and dh[0?1]. 6 group iv input signals include the following processor and l2 interface signals: ts , ar tr y , dir ty_in , and hit (when con?ured for internal l2 controller). 7 pci 3.3 v signaling environment signals are measured from 1.65 v (vdd ?2) on the rising edge of sysclk to v oh = 3.0 v or v ol = 0.3 v. pci 5 v signaling environment signals are measured from 1.65 v (vdd ?2) on the rising edge of sysclk to v oh = 2.4 v or v ol = 0.55 v. 8 group v input signals include the following bussed pci interface signals: frame , c/be [0?], ad[0?1], devsel , ird y , trd y , st op , p ar , perr , serr , lock , flshreq , and isa_master . 9 group vi input signal is the point-to-point pci gnt input signal. 10 the setup and hold time is with respect to the rising edge of hrst (see figure 4). mode select inputs include the rcs0 , foe , and dbg0 con?uration inputs. 11 t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). when the unit is given as t sysclk , the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 12 these values are guaranteed by design and are not tested.
10 mpc106 pci bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 3. input timing diagram figure 4 provides the mode select input timing diagram for the 106. figure 4. mode select input timing diagram 1.4.2.3 output ac speci?ations table 8 provides the output ac timing speci?ations for 106 (shown in table 5). assume vdd = avdd = 3.3 ?5% v dc, gnd = 0 v dc, cl = 50 pf, and 0 t j 105 ?. processor and memory interface signals are speci?d from the rising edge of the 60x bus clock (which is internally synchronized to sysclk). all units are nanoseconds. 11a vm 60x bus clock 10a 11b vm vm = midpoint voltage (1.4 v) sysclk 10b group i, ii, iii, group v and and iv inputs vi inputs vm vm = midpoint voltage (1.4 v) hrst 11c mode pins 10c
mpc106 pci bridge/memory controller hardware speci?ations 11 electrical and thermal characteristics table 8. output ac timing specifications num characteristic 66 mhz 83.3 mhz notes min max min max 12 sysclk to output driven (output enable time) 2.0 2.0 1 13a sysclk to output valid for ts and ar tr y 7.0 6.0 2, 3, 4 13b sysclk to output valid for all non-pci signals except ts , ar tr y , ras [0?], cas [0?], and dwe[0-2] 7.0 6.0 2, 3, 5 14a sysclk to output valid (for ras[0?] and cas[0?]) 7.0 6.0 2, 3 14b sysclk to output valid for pci signals 11.0 11.0 3, 6 15a sysclk to output invalid for all non-pci signals (output hold) 1.0 1.0 7, 10 15b sysclk to output invalid for pci signals (output hold) 1.0 1.0 7 18 sysclk to ar tr y high impedance before precharge (output hold) 8.0 8.0 1 19 sysclk to ar tr y precharge enable (0.4 * t sysclk ) + 2.0 (0.4 x t sysclk ) + 2.0 8, 1 21 sysclk to ar tr y high impedance after precharge (1.5 * t sysclk ) + 8.0 (1.5 x t sysclk ) + 8.0 8, 1 notes: 1 these values are guaranteed by design and are not tested. 2 output speci?ations are measured from 1.4 v on the rising edge of the appropriate clock to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin (see figure 5). 3 the maximum timing speci?ation assumes c l = 50 pf. 4 the shared outputs ts and ar tr y require pull-up resistors to hold them negated when there is no bus master driving them. 5 when the 106 is con?ured for asynchronous l2 cache srams, the dwe[0?] signals have a maximum sysclk to output valid time of (0.5 x t proc ) + 8.0 ns (where t proc is the 60x bus clock cycle time). 6 pci 3.3 v signaling environment signals are measured from 1.65 v (vdd ?2) on the rising edge of sysclk to v oh = 3.0 v or v ol = 0.3 v. 7 the minimum timing speci?ation assumes c l = 0 pf. 8 t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). when the unit is given as t sysclk the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 9 pci devices which require more than the pci-speci?d hold time of t h = 0ns or systems where clock skew approaches the pci-speci?d allowance of 2ns may not work with the mpc106. for workarounds, see motorola application note designing pci 2.1-compliant mpc106 systems (order number an1727/d).
12 mpc106 pci bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 5 provides the output timing diagram for the 106. figure 5. output timing diagram 1.4.3 jtag ac timing speci?ations table 9 provides the jtag ac timing speci?ations. assume vdd = avdd = 3.3 ?5% v dc, gnd = 0 v dc, cl = 50 pf, and 0 t j 105 ?. table 9. jtag ac timing specifications (independent of sysclk) num characteristic min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ns 2 tck clock pulse width measured at 1.4 v 20 ns 3 tck rise and fall times 0 3 ns 1 4 trst setup time to tck rising edge 10 ns 2 5 trst assert time 10 ns 1 60x bus clock 12 15a 16 16 all non-pci ts ar tr y vm vm vm = midpoint voltage (1.4v) 15a vm 18 14 13a 13 21 19 (except ts and ar tr y ) sysclk 12 15b all vm vm 14 outputs 13b pci outputs
mpc106 pci bridge/memory controller hardware speci?ations 13 electrical and thermal characteristics figure 6 provides the jtag clock input timing diagram. figure 6. jtag clock input timing diagram figure 7 provides the trst timing diagram. figure 7. trst timing diagram 6 boundary-scan input data setup time 5 ns 3 7 boundary-scan input data hold time 15 ns 3 8 tck to output data valid 0 30 ns 4 9 tck to output high impedance 0 30 ns 4 10 tms, tdi data setup time 5 ns 11 tms, tdi data hold time 15 ns 1 12 tck to tdo data valid 0 15 ns 13 tck to tdo high impedance 0 15 ns notes : 1 these values are guaranteed by design, and are not tested 2 trst is an asynchronous signal. the setup time is for test purposes only. 3 non-test signal input timing with respect to tck. 4 non-test signal output timing with respect to tck. table 9. jtag ac timing specifications (independent of sysclk) (continued) num characteristic min max unit notes tck 2 2 1 3 3 vm = midpoint voltage (1.4 v) vm vm vm 4 5 trst tck
14 mpc106 pci bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 8 provides the boundary-scan timing diagram. figure 8. boundary-scan timing diagram figure 9 provides the test access port timing diagram. figure 9. test access port timing diagram 6 7 input data valid 8 9 8 output data valid output data valid tck data inputs data outputs data outputs data outputs 10 11 input data valid 12 13 12 output data valid output data valid tck tdi, tms tdo tdo tdo
mpc106 pci bridge/memory controller hardware speci?ations 15 pin assignments 1.5 pin assignments figure 10 contains the pin assignments for the mpc106, and figure 11 provides a key to the shading. figure 11. pin assignments shading key 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 w dl26 dl28 dl30 dh31 dh29 dh27 dh25 dh23 dh21 dh19 dh17 dh15 dh13 dh11 dh9 dh7 w v dl24 dl27 dl29 dl31 dh30 dh28 dh26 dh24 dh20 dh18 dh16 dh14 dh12 dh10 dh8 dl22 v u ma1/ sdba0/ ar9 dl23 dl25 dl14 pll2 pll0 dl12 dl10 dl4 dl2 dl0 doe / dbgl2 t oe dbg1 dh6 dl21 dl20 u t ma2/ sdma2/ ar10 we dh0 dl15 pll3 pll1 dl13 dl11 dl3 dl1 tv/ br2 ba0/ br3 hit dir ty_in / br1 dl19 dcs / bg3 t r ma3/ sdma3/ ar11 rcs0 dh2 dh1 dl16 vss vdd dl9 dl5 vss vdd twe / bg2 dir ty_out / bg1 ads / dale/ brl2 a0 ts r p ma5/ sdma5/ ar13 ma4/ sdma4/ ar12 dh4 dh3 vss vdd vss dl8 dl6 vdd vss vdd ba1/ baa / bgl2 d we0 / dbg2 a1 xa ts /sdma 1 p n ma6/ sdma6/ ar14 ma0/ sdba1/ sdma0/ ar0 dl17 dh5 vdd vss vdd dl7 dh22 vss vdd vss lbclaim ci a2 t a n m ma8/ sdma8/ ar16 ma7/ sdma7/ ar15 ras0 / cs0 dl18 vss vdd vss nc nc vdd vss vdd wt gbl a3 tt4 m l hrst ma9/ sdma9/ ar17 qa ck ras1 / cs1 vdd cko/ dwe2 ras5 / cs5 vss vdd vss sysclk dbg0 tbst br0 a4 tt3 l k ma11/ sdma11/ ar19 ma10/ sdma10/ ar18 ras3 / cs3 ras2 / cs2 ras4 / cs4 ras7 / cs7 vdd avdd vss vdd a9 a8 a7 bg0 a5 tt2 k j ma12/ sdma12/ ar20 cas0 / dqm0 ppen rcs1 ras6 / cs6 mcp dbglb / cke vss vdd vss a11 a6 a13 a12 a10 tea j h qreq cas1 / dqm1 suspend trst vss d we1 / dbg3 pirq / sdras nc nc vdd vss vdd a15 a14 a16 tt1 h g cas2 / dqm2 rtc cas4 / dqm4 cas5 / dqm5 vdd lssd_mode vdd par lock vss vdd vss tsiz1 tsiz0 a17 tt0 g f bctl0 bctl1 cas6 / dqm6 tck vss vdd vss perr devsel vdd vss vdd a21 tsiz2 ar tr y a18 f e cas3 / dqm3 nmi cas7 / dqm7 mdle / sdcas tdo vss vdd serr ird y vss vdd a31 a29 a22 a20 a19 e d par0/ ar1 par1/ ar2 tms foe ad28 ad24 ad21 ad17 ad14 ad10 c/be0 ad4 ad0 a30 aa ck a23 d c par2/ ar3 par3/ ar4 par5/ ar6 ad30 ad26 ad23 ad19 c/be2 c/be1 ad12 ad8 ad6 ad2 a27 a25 a24 c b par4/ ar5 par7/ ar8 ad1 tdi ad7 ad11 ad15 trd y ad18 ad22 ad25 ad29 req isa_master / berr a28 a26 b a par6/ ar7 gnt ad3 ad5 ad9 ad13 frame st op ad16 ad20 c/be3 ad27 ad31 flshreq mema ck a 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 figure 10. pin assignments nc vss vdd no connect power supply ground power supply positive avdd clock power supply positive (k9) view signals
16 mpc106 pci bridge/memory controller hardware speci?ations pinout listings 1.6 pinout listings table 10 provides the pinout listing for the mpc106. s ome signals have dual functions and are shown more than once. table 10. pinout listing signal name pin number active i/o 60x processor interface signals a[0?1] r2, p2, n2, m2, l2, k2, j5, k4, k5, k6, j2, j6, j3, j4, h3, h4, h2, g2, f1, e1, e2, f4, e3, d1, c1, c2, b1, c3, b2, e4, d3, e5 high i/o aa ck d2 low i/o ar tr y f2 low i/o bg0 k3 low output bg1 (dir ty_out ) r4 low output bg2 (twe) r5 low output bg3 (dcs ) t1 low output br0 l3 low input br1 (dir ty_in ) t3 low input br2 (tv) t6 low input br3 (ba0) t5 low input ci n3 low i/o dbg0 l5 low output dbg1 (t oe ) u4 low output dbg2 (d we0 ) p3 low output dbg3 (d we1 ) h11 low output dbglb (cke) j10 low output dh[0?1] t14, r13, r14, p13, p14, n13, u3, w1, v2, w2, v3, w3, v4, w4, v5, w5, v6, w6, v7, w7, v8, w8, n8, w9, v9, w10, v10, w11, v11, w12, v12, w13 high i/o dl[0?1] u6, t7, u7, t8, u8, r8, p8, n9, p9, r9, u9, t9, u10, t10, u13, t13, r12, n14, m13, t2, u1, u2, v1, u15, v16, u14, w16, v15, w15, v14, w14, v13 high i/o gbl m3 low i/o
mpc106 pci bridge/memory controller hardware speci?ations 17 pinout listings lbclaim n4 low input mcp j11 low output t a n1 low i/o tbst l4 low i/o tea j1 low output ts r1 low i/o tsiz[0?] g3, g4, f3 high i/o tt[0?] g1, h1, k1, l1, m1 high i/o wt m4 low i/o xa ts (sdma1) p1 low input l2 cache interface signals ads /d ale /brl2 r3 low i/o ba0 (br3 ) t5 low output ba1/baa /bgl2 p4 low output dbgl2 /doe u5 low output dcs (bg3 ) t1 low output dir ty_in (br1 ) t3 low input dir ty_out (bg1 ) r4 low output d we0 (dbg2 ) p3 low output d we1 (dbg3) h11 low output d we2 (cko) l11 low output hit t4 low input t oe (dbg1 ) u4 low output tv (br2 ) t6 high i/o twe (bg2 ) r5 low output memory interface signals bctl [0?] f16, f15 low output berr (isa_master ) b3 low input table 10. pinout listing (continued) signal name pin number active i/o
18 mpc106 pci bridge/memory controller hardware speci?ations pinout listings cas /dqm[0?] j15, h15, g16, e16, g14, g13, f14, e14 low output cke/dbglb j10 high output foe d13 low output ma0/sdba1/sdma0/ar0 n15 high output sdma1 (xa ts ) p1 high output ma1/sdba0/ar9 u16 high output ma[2?2]/sdma[2?2]/ar [10?0] t16, r16, p15, p16, n16, m15, m16, l15, k15, k16, j16 high output mdle /sdcas e13 low output par[0?]/ar[1?] d16, d15, c16, c15, b16, c14, a16, b15 high i/o ppen j14 low output ras /cs [0?] m14, l13, k13, k14, k12, l10, j12, k11 low output rcs0 r15 low i/o rcs1 j13 low output rtc g15 high input sdras (pirq ) h10 low output we t15 low output pci interface signals1 ad[31?] a4, c13, b5, d12, a5, c12, b6, d11, c11, b7, d10, a7, c10, b8, d9, a8, b10, d8, a11, c7, b11, d7, a12, c6, b12, c5, a13, d5, a14, c4, b14, d4 high i/o c/be [3?] a6, c9, c8, d6 low i/o devsel f8 low i/o flshreq a3 low input frame a10 low i/o gnt a15 low input ird y e8 low i/o isa_master (berr) b3 low input lock g8 low input mema ck a2 low output par g9 high i/o perr f9 low i/o pirq (sdras ) h10 low output req b4 low output table 10. pinout listing (continued) signal name pin number active i/o
mpc106 pci bridge/memory controller hardware speci?ations 19 pinout listings serr e9 low i/o st op a9 low i/o trd y b9 low i/o interrupt, clock, and power management signals cko (d we2 ) l11 high output hrst l16 low input nmi e15 high input qa ck l14 low output qreq h16 low input sysclk l6 clock input suspend h14 low input test/con?uration signals pll[0?] u11, t11, u12, t12 high input tck f13 clock input tdi b13 high input tdo e12 high output tms d14 high input trst h13 low input power and ground signals avdd k9 high clock power lssd_mode 2 g11 low input vdd e10, e6, f11, f5, f7, g10, g12, g6, h5, h7, k10, k7, l12, m11, m5, m7, n10, n12, n6, p11, p5, p7, r10, r6, j8, l8 high power vss e11, e7, f10, f12, f6, g5, g7, h12, h6, j7, l7, m10, m12, m6, n11, n5, n7, p10, p12, p6, r11, r7, k8, j9, l9 low ground nc h8, h9, m8, m9 note: 1 all pci signals are in little-endian bit order. 2 this test signal is for factory use only. it must be pulled up to vdd for normal device operation. table 10. pinout listing (continued) signal name pin number active i/o
20 mpc106 pci bridge/memory controller hardware speci?ations package description 1.7 package description the following sections provide the package parameters and the mechanical dimensions for the 106. 1.7.1 package parameters the package parameters are as provided in the following list. the package type is a 21 mm x 25 mm, 304-lead c4 ceramic ball grid array (cbga). package outline 21 mm x 25 mm interconnects 303 (16 x 19 ball array minus one) pitch 1.27 mm solder attach 63/37 sn/pb solder balls 10/90 sn/pb, 0.89 mm diameter maximum module height 3.16 mm co-planarity speci?ation 0.15 mm
mpc106 pci bridge/memory controller hardware speci?ations 21 package description 1.7.2 mechanical dimensions figure 12 shows the mechanical dimensions for the mpc106. figure 12. mechanical dimensions c a1 0.200 2x 0.200 2x ?e ?f 0.150 ?t t h g k ? 0.300 12 345678910111213141516 w v u t r p n m l k j h g f e d c b a 303x ? d s t s e s f ? 0.150 s t *not to scale note: all measurements are in mm. min max a 25.0 basic b 21.0 basic c 2.3 3.16 d 0.82 0.93 g 1.27 basic h 0.79 0.99 k 0.635 basic n 5.8 6.0 p 7.2 7.4 top view bottom view p b a n
22 mpc106 pci bridge/memory controller hardware speci?ations system design information 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the 106. 1.8.1 pll con?uration the 106 requires a single system clock input, sysclk. the sysclk frequency dictates the frequency of operation for the pci bus. an internal pll on the mpc106 generates a master clock that is used for all of the internal (core) logic. the master clock provides the core frequency reference and is phase-locked to the sysclk input. the 60x processor, l2 cache, and memory interfaces operate at the core frequency. in the 5:2 clock mode (rev. 4.0 only), the mpc106 needs to sample the 60x bus clock (on the lbclaim con?uration input) to resolve clock phasing with the pci bus clock (sysclk). the pll is con?ured by the pll[0?] signals. for a given sysclk (pci bus) frequency, the clock mode con?uration signals (pll[0?]) set the core frequency (and the frequency of the vco controlling the pll lock). the supported core and vco frequencies and the corresponding pll[0?] settings are provided in table 11. table 11. pll configuration pll[0?] 1 core/syscl k ratio vco multiplier core frequency (vco frequency) in mhz pci bus 16.6 mhz pci bus 20 mhz pci bus 25 mhz pci bus 33.3 mhz 0001 1:1 x4 33.3 (133) 0100 2:1 x2 66.6 (133) 0101 2:1 x4 33.3 (133) 40 (160) 50 (200) 0110 5:2 2 x2 83.3 (166) 0111 5:2 2 x4 41.6 (166) 1000 3:1 x2 60(120) 75 (150) 0011 pll-bypass 3 pll off sysclk clocks core circuitry directly 1x core/sysclk ratio implied 1111 clock off 4 pll off no core clocking occurs notes : 1 pll[0?] settings not listed are reserved. some pll con?urations may select bus, cpu, or vco frequencies which are not useful, not supported, or not tested. see section 1.4.2.1, ?lock ac speci?ations, for valid sysclk and vco frequencies. 2 5:2 clock modes are only supported by mpc106 rev 4.0; earlier revisions do not support 5:2 clock modes. the 5:2 modes require a 60x bus clock applied to the 60x clock phase (lbclaim ) con?uration input signal during power-on reset, hard reset, and coming out of sleep and suspend power-saving modes. 3 in pll-bypass mode, the sysclk input signal clocks the internal circuitry directly, the pll is disabled, and the core/sysclk ratio is set for 1:1 mode operation. this mode is intended for factory use and third-party tool vendors only. note also : the ac timing speci?ations given in this document do not apply in pll-bypass mode. 4 in clock-off mode, no clocking occurs inside the mpc106 regardless of the sysclk input. 5 pll[0-3] = 0010 (2:1 core/sysclk ratio; x8 vco multiplier) exists on the chip but will fail to lock 50% of the time. therefore, this con?uration should not be used and 1:1 modes between 16-25mhz are not supported.
mpc106 pci bridge/memory controller hardware speci?ations 23 system design information 1.8.2 pll power supply filtering the avdd power signal is provided on the 106 to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the avdd input signal should be ?tered using a circuit similar to the one shown in figure 13. the circuit should be placed as close as possible to the avdd pin to ensure it ?ters out as much noise as possible. figure 13. pll power supply filter circuit 1.8.3 decoupling recommendations due to the 106s large address and data buses and high operating frequencies, it can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the system, and the 106 itself requires a clean, tightly regulated source of power. it is strongly recommended that the system design include six to eight 0.1 f (ceramic) and 10 f (tantalum) decoupling capacitors to provide both high- and low-frequency ?tering. these capacitors should be placed closely around the perimeter of the 106 package (or on the underside of the pcb). it is also recommended that these decoupling capacitors receive their power from separate vdd and gnd power planes in the pcb, utilizing short traces to minimize inductance. only surface mount technology (smt) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd plane, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low equivalent series resistance (esr) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?00 f (avx tps tantalum) or 330 f (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied (using pull-up resistors) to vdd. unused active high inputs should be tied (using pull-down resistors) to gnd. all no-connect (nc) signals must remain unconnected. power and ground connections must be made to all external vdd, avdd, and gnd pins of the 106. 1.8.4.1 pull-up resistor recommendations the mpc106 requires pull-up (or pull-down) resistors on several control signals of the 60x and pci buses to maintain the control signals in the negated state after they have been actively negated and released by the 106 or other bus masters. the jtag test reset signal, trst , should be pulled down during normal system operation. also, as indicated in table 10, the factory test signal, lssd_mode , must be pulled up for normal device operation during inactive periods on the bus, the address and transfer attributes on the bus (a[0?1], tt[0?], tbst , wt , ci , and gbl ) are not driven by any master and may ?at in the high-impedance state for relatively long periods of time. since the mpc106 must continually monitor these signals, this ?at vdd avdd 10 ? 10 ? 0 . 1 ? gnd (3.3 v)
24 mpc106 pci bridge/memory controller hardware speci?ations system design information condition may cause excessive power draw by the input receivers on the mpc106 or by other receivers in the system. it is recommended that these signals be pulled up or restored in some manner by the system. the 60x data bus input receivers on the mpc106 do not require pull-up resistors on the data bus signals (dh[0?1], dl[0?1], and par[0?]). however, other data bus receivers in the system may require pull-up resistors on these signals. in general, the 60x address and control signals are pulled up to 3.3 vdc and the pci control signals are pulled up to 5 vdc through weak (2?0 k ? ) resistors. resistor values may need to be adjusted stronger to reduce induced noise on speci? board designs. table 12 summarizes the pull-up/pull-down recommendations for the mpc106. 1.8.5 thermal management information this section provides thermal management information for the c4/cbga package. proper thermal control design is primarily dependent on the system-level design. the use of c4 die on a cbga interconnect technology offers signi?ant reduction in both the signal delay and the microelectronic packaging volume. figure 14 shows the salient features of the c4/cbga interconnect technology. the c4 interconnection provides both the electrical and the mechanical connections for the die to the ceramic substrate. after the c4 solder bump is re?wed, epoxy (encapsulant) is under-?led between the die and the substrate. under-?l material is commonly used on large high-power die; however, this is not a requirement of the c4 technology. the package substrate is a multilayer-co?ed ceramic. the package-to-board interconnection is by an array of orthogonal 90/10 (lead/tin) solder balls on 1.27 mm pitch. during assembly of the c4/cbga package to the board, the high-melt balls do not collapse. table 12. pull-up/pull-down recommendations signal type signals pull-up/pull-down 60x bus control br n ts , xa ts , aa ck ar tr y t a pull up to 3.3 vdc 60x bus address/transfer attributes a[0?1], tt[0?], tbst wt , ci , gbl pull up to 3.3 vdc cache control ads pull up to 3.3 vdc hit, tv pull up to 3.3 vdc or pull-down to gnd depending on programmed polarity pci bus control req frame , ird y devsel , trd y , st op serr , perr lock flshreq , isa_master . typically pull up to 5 vdc note: for closed systems not requiring 5v power, these may be pulled up to 3.3 vdc. jtag trst pull down to gnd (during normal system operation) factory test lssd_mode pull up to 3.3 vdc
mpc106 pci bridge/memory controller hardware speci?ations 25 system design information figure 14. exploded cross-sectional view 1.8.5.1 internal package conduction resistance for this c4/cbga packaging technology, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case thermal resistance the die junction-to-lead thermal resistance these parameters are shown in table 13. in this c4/cbga package, the silicon chip is exposed; therefore, the package ?ase?is the top of the silicon. figure 15 provides a simpli?d thermal network in which a c4/cbga package is mounted to a printed-circuit board. figure 15. c4/cbga package mounted to a printed-circuit board table 13. thermal resistance thermal metric effective thermal resistance junction-to-case thermal resistance 0.133 ?/w junction-to-lead (ball) thermal resistance 3.8 ?/w chip with c4 encapsulant ceramic substrate cbga joint printed-circuit board external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
26 mpc106 pci bridge/memory controller hardware speci?ations system design information 1.8.5.2 board and system-level modeling a common ?ure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies is the junction-to-ambient thermal resistance. the ?al chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the components power consumption, a number of factors affect the ?al operating die-junction temperature. for example, these factors might include air?w, board population, heat sink ef?iency, heat sink attach, next-level interconnect technology, and system air temperature rise. due to the complexity and the many variations of system-level boundary conditions for todays microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for this reason, we recommend using conjugate heat transfer models for the board as well as system-level designs. to expedite system-level thermal analysis, several ?ompact cbga thermal models are available on request within flotherm . the die junction-to-ambient thermal resistance is shown in table 14. the model results are in accordance with semi speci?ation g38. this standard speci?s a single component be placed on a 7.5 cm x 10 cm single-layer printed-circuit card. note that this single metric may not adequately describe three-dimensional heat ?w. table 14. die junction-to-ambient thermal resistance air?w velocity (meter/second) air?w velocity (feet/minute) die junction-to-ambient thermal resistance (semi g38) (?/w) 1 196.8 22.0 2 393.7 18.5 3 590.0 17.0
mpc106 pci bridge/memory controller hardware speci?ations 27 document revision history 1.9 document revision history table 15 lists signi?ant changes between revisions of this document. table 15. document revision history document revision substantive change(s) rev 0 initial release rev 1 changed vco maximum frequency in table 6 to 200 mhz changed input and hi-z leakage current in table 4. from 10? to 15? changed i oh and i ol in table 4 from 18ma and 14ma respectively to -7ma and 7ma to correct the sign and reduce the current to worst case value for the lowest strength default driver changed footnote 4 to table 6 to be consistent with sysclk jitter spec of 200ps modi?d table 7, figure 3, table 8, and figure 5 to clarify reference clock (60x bus clock or sysclk) for input and output speci?ations changed group i and group ii signals input setup requirement for 83 mhz in table 7 from 3.0 ns to 3.5 ns min. changed group i-iv (non-pci signals) input hold requirement (spec 11a) in table 7 from 1.0 ns to 0 ns changed group v and vi (pci signals) input hold requirement (spec 11b) in table 7 from 1.0ns to -0.5ns changed output valid times for all non-pci signals (specs 13a, 13b and 14a) from 8 ns to 7 ns at 66 mhz and from 7 ns to 6 ns at 83 mhz corrected figure 10 to re?ct toe signal is shared with dbg1 on pin u5 rev 2 changed input and hi-z leakage current, v in in table 4 from 5.5v to 3.3v changed the power consumption data in table 5 changed note 7 of table 8 to show the minimum timing speci?ation assumes cl=0 pf rev 3 deleted pll[0-3] = 0010 from table 11 to remove 1:1 mode operation between 16mhz and 25mhz added note 10 to table 8 regarding pci hold time lowered pci 3.3v signalling output high voltage from 3.0 v to 2.7v and added current conditions for pci 3.3v voh and vol in table 4 to re?ct current production test included note 12 in speci?ation 10c of table 4; clari?d note 9 in table 8 and included in speci?ation 12 and 18; added a similar ?uaranteed by design and not tested note to table 9 and included in speci?ations 3, 7, and 11. all to re?ct current production test. corrected figure 12 dimensions from tbd to actual die size table 1 and table 2 include notes on extended temperature parts. rev 4 table 8, note 8 changed to include: ?hese values are guaranteed by design and are not tested. rev 5 added pns references below table 1 and table 6. changed footnote ordering in table 8, table 9, and table 10. added new footnote 2 to table 6. changed part number key.
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual perfor mance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical ex perts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or autho rized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, o r for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer pu rchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employe es, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that moto rola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440 -3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n .t., hong kong. 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625, attn: risc applications engineering world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm http://www.motorola.com/coldfire mpc106ec/d digitaldna is a trademark of motorola, inc. the powerpc name, the powerpc logotype, and powerpc 603e are trademarks of international business machines corporation used by motorola under license from international business machines corporation. 1.10 ordering information figure 16 provides the motorola part-numbering nomenclature for the 106. in addition to the core frequency, the part numbering scheme also consists of a part modi?r and application modi?r. the part modi?r indicates any enhancements in the part from the original production design. the application modi?r may specify special bus frequencies or application conditions. each part number also contains a revision code. this refers to the die mask revision number and is speci?d in the part-numbering scheme for identi?ation purposes only. pr mpc 106 a rx xx x x product code part identi?r part modi?r package frequency application modi?r revision level 2 rx = bga 66 or 83 c no 5:2 mode d 5:2 mode t extended temperature 1 e 3.0 g 4.0 notes: 1 see part number speci?ations (mpc106arxtgpns/d). 2 for current revision level, contact local motorola sales of?e. figure 16. part number key

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